857 search results - page 63 / 172 » Implementing a STARI chip |
ISCAS
2007
IEEE
15 years 4 months ago
2007
IEEE
—The paper presents a novel architecture for a direct digital frequency synthesizer (DDFS) based on the QuasiLinear interpolation (QLIP) method. The four-segment QLIP is utilized...
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
—Associated with the ever growing integration scales is the increase in process variability. In the context of networkon-chip, this variability affects the maximum frequency that...
ICES
1998
Springer
15 years 2 months ago
1998
Springer
In this paper we present a new chromosome representation for evolving digital circuits. The representation is based very closely on the chip architecture of the Xilinx 6216 FPGA. W...
DAGSTUHL
2007
14 years 11 months ago
2007
Abstract. Two ways to exploit chips with a very large number of transistors are multicore processors and programmable logic chips. Some data parallel algorithms can be executed eï¬...
IPPS
2010
IEEE
14 years 7 months ago
2010
IEEE
It is possible to implement the parallel random access machine (PRAM) on a chip multiprocessor (CMP) efficiently with an emulated shared memory (ESM) architecture to gain easy par...