857 search results - page 64 / 172 » Implementing a STARI chip |
ICASSP
2011
IEEE
14 years 1 months ago
2011
IEEE
In this paper the authors are addressing the concerns associated with fast growing DSP chips and tools and the impact they have on teaching DSP implementation. The authors also pr...
TVLSI
2002
14 years 9 months ago
2002
Gate diffusion input (GDI)--a new technique of low-power digital combinatorial circuit design--is described. This technique allows reducing power consumption, propagation delay, an...
DCC
2010
IEEE
14 years 8 months ago
2010
IEEE
This work proposes a novel practical and general-purpose lossless compression algorithm named Neural Markovian Predictive Compression (NMPC), based on a novel combination of Bayesi...
ECCTD
2011
13 years 9 months ago
2011
⎯ Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate th...
IJPP
2006
14 years 9 months ago
2006
Chip multiprocessors hold great promise for achieving scalability in future systems. Microthreaded chip multiprocessors add a means of exploiting legacy code in such systems. Usin...