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» Implementing a STARI chip
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ICCD
1992
IEEE
82views Hardware» more  ICCD 1992»
15 years 1 months ago
A Comparison of Self-Timed Design Using FPGA, CMOS, and GaAs Technologies
Asynchronous or self-timed systems that do not rely on a global clock to keep system components synchronized can offer significant advantages over traditional clocked circuits in ...
Erik Brunvand, Nick Michell, Kent F. Smith
DATE
2010
IEEE
153views Hardware» more  DATE 2010»
14 years 8 months ago
Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem
— Applications like 4G baseband modem require single-chip implementation to meet the integration and power consumption requirements. These applications demand a high computing pe...
Camille Jalier, Didier Lattard, Ahmed Amine Jerray...
HICSS
2006
IEEE
164views Biometrics» more  HICSS 2006»
15 years 3 months ago
A Methodology for Generating Application-Specific Heterogeneous Processor Arrays
Hardware designers are increasingly turning to Single Chip Multi-Processors to achieve power and throughput goals. To further increase performance for a specific application the c...
Stephen D. Craven, Cameron Patterson, Peter M. Ath...
ISCA
1994
IEEE
104views Hardware» more  ISCA 1994»
15 years 1 months ago
Exploring the Design Space for a Shared-Cache Multiprocessor
In the near future, semiconductor technology will allow the integration of multiple processors on a chip or multichipmodule (MCM). In this paper we investigate the architecture an...
Basem A. Nayfeh, Kunle Olukotun
MASCOTS
2007
14 years 11 months ago
A Novel Flow Control Scheme for Best Effort Traffic in NoC Based on Source Rate Utility Maximization
—Advances in semiconductor technology, has enabled designers to put complex, massively parallel multiprocessor systems on a single chip. Network on Chip (NoC) that supports high ...
Mohammad Sadegh Talebi, Fahimeh Jafari, Ahmad Khon...