857 search results - page 69 / 172 » Implementing a STARI chip |
TVLSI
2002
14 years 9 months ago
2002
The implementation of a microcoded elliptic curve processor using field-programmable gate array technology is described. This processor implements optimal normal basis field operat...
DSD
2010
IEEE
14 years 7 months ago
2010
IEEE
Until a decade ago, the concept of phased array beamforming was mainly implemented with mechanical or analog solutions. Today, digital hardware has become powerful enough to perfor...
113
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ERSA
2010
14 years 7 months ago
2010
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...
146
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ASAP
2011
IEEE
2011
IEEE
High-throughput Contention-Free concurrent interleaver architecture for multi-standard turbo decoder
13 years 9 months ago
—To meet the higher data rate requirement of emerging wireless communication technology, numerous parallel turbo decoder architectures have been developed. However, the interleav...
CHES
2011
Springer
13 years 9 months ago
2011
Springer
A lightweight and secure key storage scheme using silicon Physical Unclonable Functions (PUFs) is described. To derive stable PUF bits from chip manufacturing variations, a lightwe...