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» Implementing a STARI chip
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ISCA
2007
IEEE
182views Hardware» more  ISCA 2007»
15 years 4 months ago
Configurable isolation: building high availability systems with commodity multi-core processors
High availability is an increasingly important requirement for enterprise systems, often valued more than performance. Systems designed for high availability typically use redunda...
Nidhi Aggarwal, Parthasarathy Ranganathan, Norman ...
ISCAS
2006
IEEE
133views Hardware» more  ISCAS 2006»
15 years 3 months ago
Neuronal ion-channel dynamics in silicon
Abstract— We present a simple silicon circuit for modelling voltagedependent ion channels found within neural cells, capturing both the gating particle’s sigmoidal activation (...
Kai M. Hynna, Kwabena Boahen
CODES
2002
IEEE
15 years 2 months ago
Hardware support for real-time embedded multiprocessor system-on-a-chip memory management
The aggressive evolution of the semiconductor industry — smaller process geometries, higher densities, and greater chip complexity — has provided design engineers the means to...
Mohamed Shalan, Vincent John Mooney III
MICRO
2008
IEEE
126views Hardware» more  MICRO 2008»
14 years 9 months ago
Multicore Resource Management
UAL PRIVATE MACHINE ABSTRACTION WOULD ALLOW SOFTWARE POLICIES TO EXPLICITLY MANAGE MICROARCHITECTURE RESOURCES. VPM POLICIES, IMPLEMENTED PRIMARILY IN SOFTWARE, TRANSLATE APPLICATI...
Kyle J. Nesbit, Miquel Moretó, Francisco J....
JNCA
2007
80views more  JNCA 2007»
14 years 9 months ago
High-speed routers design using data stream distributor unit
As the line rates standards are changing frequently to provide higher bit rates, the routers design has become very challenging due to the need for new wire-speed router’s netwo...
Ali El Kateeb