857 search results - page 76 / 172 » Implementing a STARI chip |
GLVLSI
2002
IEEE
15 years 2 months ago
2002
IEEE
This paper describes a new design for a hardware accelerator to support grid-based Maze Routing. Based on the direct mapped approach of Breuer and Shamsa [3], this work refines th...
ICPP
1991
IEEE
15 years 1 months ago
1991
IEEE
This paper presents an architecture for programmable systolic arrays that provides simple and e cient systolic communication. The Brown Systolic Array is a linear implementation o...
NIPS
1996
14 years 11 months ago
1996
We describe the implementation of a hidden Markov model state decoding system, a component for a wordspotting speech recognition system. The key specification for this state decod...
DT
2002
14 years 9 months ago
2002
This article presents an in-circuit emulation (ICE) module that can be embedded with a microprocessr core. The ICE module, based on the IEEE 1149.1 JTAG architecture, supports typ...
ISQED
2010
IEEE
14 years 8 months ago
2010
IEEE
Multiple use-case chip multiprocessor (CMP) applications require adaptive on-chip communication fabrics to cope with changing use-case performance needs. Networks-on-chip (NoC) ha...