Sciweavers

857 search results - page 78 / 172
» Implementing a STARI chip
Sort
View
FAST
2011
14 years 1 months ago
Reliably Erasing Data from Flash-Based Solid State Drives
Reliably erasing data from storage media (sanitizing the media) is a critical component of secure data management. While sanitizing entire disks and individual files is well-unde...
Michael Yung Chung Wei, Laura M. Grupp, Frederick ...
ETS
2011
IEEE
212views Hardware» more  ETS 2011»
13 years 9 months ago
Structural Test for Graceful Degradation of NoC Switches
Abstract—Networks-on-Chip (NoCs) are implicitly fault tolerant due to their inherent redundancy. They can overcome defective cores, links and switches. As a side effect, yield is...
Atefe Dalirsani, Stefan Holst, Melanie Elm, Hans-J...
EUROSYS
2007
ACM
15 years 7 months ago
Thread clustering: sharing-aware scheduling on SMP-CMP-SMT multiprocessors
The major chip manufacturers have all introduced chip multiprocessing (CMP) and simultaneous multithreading (SMT) technology into their processing units. As a result, even low-end...
David K. Tam, Reza Azimi, Michael Stumm
IPPS
2003
IEEE
15 years 3 months ago
Parallel Direct Solution of Linear Equations on FPGA-Based Machines
The efficient solution of large systems of linear equations represented by sparse matrices appears in many tasks. LU factorization followed by backward and forward substitutions i...
Xiaofang Wang, Sotirios G. Ziavras
SAC
2008
ACM
14 years 9 months ago
Offline count-limited certificates
In this paper, we present the idea of offline count-limited certificates (or clics for short), and show how these can be implemented using minimal trusted hardware functionality a...
Luis F. G. Sarmenta, Marten van Dijk, Jonathan Rho...