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» Implementing a STARI chip
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ICESS
2007
Springer
15 years 10 months ago
Memory Offset Assignment for DSPs
Compact code generation is very important for an embedded system that has to be implemented on a chip with a severely limited amount of size. Even though on-chip data memory optimi...
Jinpyo Hong, J. Ramanujam
SBCCI
2006
ACM
97views VLSI» more  SBCCI 2006»
15 years 10 months ago
An ultra low-power class-AB sinh integrator
A new ultra low-power Class-AB Sinh integrator is proposed here. The translinear companding integrator is based on hyperbolic-sine transconductors and uses only one grounded capac...
Sandro A. P. Haddad, Wouter A. Serdijn
ASYNC
2005
IEEE
96views Hardware» more  ASYNC 2005»
15 years 9 months ago
GasP Control for Domino Circuits
We present two novel asynchronous control circuits for domino pipelines. The control circuits are based on GasP circuits, have a minimum cycle time of six gate delays, and compare...
Jo C. Ebergen, Jonathan Gainsley, Jon K. Lexau, Iv...
EH
2003
IEEE
84views Hardware» more  EH 2003»
15 years 9 months ago
Evolved Reversible Cascades Realized on the CAM-Brain Machine
This paper presents a new approach to reversible cascade evolution based on a 3D cellular automaton. As a research platform we used the ATR’s CAMBrain Machine (CBM). Reversible ...
Andrzej Buller, Marek A. Perkowski
FPL
2003
Springer
136views Hardware» more  FPL 2003»
15 years 9 months ago
FPGAs for High Accuracy Clock Synchronization over Ethernet Networks
This article describes the architecture and implementation of two systems on a programmable chip, which support high accuracy clock synchronization over Ethernet networks. The netw...
Roland Höller