857 search results - page 83 / 172 » Implementing a STARI chip |
GECCO
2003
Springer
15 years 3 months ago
2003
Springer
Associative memories based on DNA-affinity have been proposed [2]. Here, the performance, efficiency, reliability of DNA-based memories is quantified through simulations in silico....
ICCAD
1994
IEEE
15 years 1 months ago
1994
IEEE
For a logic design with level-sensitive latches, we need to validate timing signal paths which may flush through several latches. We developed efficient algorithms based on the mo...
DATE
2004
IEEE
15 years 1 months ago
2004
IEEE
This paper presents an overview of an assembler driven verification methodology (ADVM) that was created and implemented for a chip card project at Infineon Technologies AG [2]. Th...
FCCM
2004
IEEE
15 years 1 months ago
2004
IEEE
This paper describes the package of test bench code required to verify the Algotronix' AES IP Core. Several authors (see the references in [3]) have published papers detailing...
ERSA
2006
14 years 11 months ago
2006
To date, some types of Optically Reconfigurable Gate Arrays (ORGAs) have been developed to realize capabilities of rapid reconfiguration with numerous reconfiguration contexts. How...