Sciweavers

857 search results - page 84 / 172
» Implementing a STARI chip
Sort
View
JCP
2008
120views more  JCP 2008»
15 years 4 months ago
High Throughput VLSI Architecture for Blackman Windowing in Real Time Spectral Analysis
This paper presents a high throughput VLSI architecture for Blackman windowing. Since most of the implementation of windowing functions for real time applications, are based on eit...
Kailash Chandra Ray, A. S. Dhar
IJBC
2007
39views more  IJBC 2007»
15 years 4 months ago
Optimal CNN Templates for Linearly-Separable One-Dimensional Cellular Automata
In this tutorial, we present optimal Cellular Nonlinear Network (CNN) templates for implementing linearly-separable one-dimensional (1-D) Cellular Automata (CA). From the gallery ...
P. J. Chang, Bharathwaj Muthuswamy
EWSN
2009
Springer
16 years 4 months ago
secFleck: A Public Key Technology Platform for Wireless Sensor Networks
We describe the design and implementation of a public-key platform, secFleck, based on a commodity Trusted Platform Module (TPM) chip that extends the capability of a standard node...
Wen Hu, Peter I. Corke, Wen Chan Shih, Leslie Over...
VLSID
2005
IEEE
149views VLSI» more  VLSID 2005»
16 years 4 months ago
ADOPT: An Approach to Activity Based Delay Optimization
: The direct result of shrinking devices is not only higher densities but also increased switching activity and thus higher device temperatures. The variation in temperature over t...
Gaurav Arora, Abhishek Sharma, D. Nagchoudhuri, M....
ITNG
2007
IEEE
15 years 10 months ago
FPGA-based Vector Processing for Matrix Operations
A programmable vector processor and its implementation with a field-programmable gate array (FPGA) are presented. This processor is composed of a vector core and a tightly couple...
Hongyan Yang, Sotirios G. Ziavras, Jie Hu