857 search results - page 86 / 172 » Implementing a STARI chip |
CAL
2007
14 years 9 months ago
2007
—The design of scalable and reliable interconnection networks for multicore chips (NoCs) introduces new design constraints like power consumption, area, and ultra low latencies. ...
JCM
2008
14 years 9 months ago
2008
With the feature size of semiconductor technology reducing and intellectual properties (IP) cores increasing, on chip communication architectures have a great influence on the perf...
ISBI
2007
IEEE
15 years 4 months ago
2007
IEEE
Emerging multi-core processors are able to accelerate medical imaging applications by exploiting the parallelism available in their algorithms. We have implemented a mutual-inform...
DAC
2002
ACM
15 years 10 months ago
2002
ACM
In this paper, we introduce a framework to estimate the power consumption on switch fabrics in network routers. We propose different modeling methodologies for node switches, inte...
HPCA
2003
IEEE
15 years 10 months ago
2003
IEEE
To sustain instruction throughput rates in more aggressively clocked microarchitectures, microarchitects have incorporated larger and more complex branch predictors into their des...