857 search results - page 88 / 172 » Implementing a STARI chip |
FPL
2007
Springer
15 years 4 months ago
2007
Springer
Reconfigurable computing entails the utilization of a generalpurpose processor augmented with a reconfigurable hardware structure (usually an FPGA). Normally, a complete recon...
FPL
2007
Springer
15 years 4 months ago
2007
Springer
In this paper, we present a shared instruction and data memory controller for the On-Chip Memory (OCM) bus of the PowerPC embedded in the Virtex-4 chip. The traditional design of ...
GECCO
2007
Springer
15 years 4 months ago
2007
Springer
This work presents a novel approach to filter synthesis on a field programmable analog array (FPAA) architecture using a genetic algorithm (GA). First, a Matlab model of the FPA...
DSD
2006
IEEE
15 years 3 months ago
2006
IEEE
System Level Design (SLD) is widely seen as a solution for bridging the gap between chip complexity and design productivity of Systems on Chip (SoC). SLD relieves the designer fro...
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ACMMSP
2006
ACM
15 years 3 months ago
2006
ACM
This paper proposes and studies a distributed L2 cache management approach through page-level data to cache slice mapping in a future processor chip comprising many cores. L2 cach...