Sciweavers

857 search results - page 89 / 172
» Implementing a STARI chip
Sort
View
FCCM
2005
IEEE
115views VLSI» more  FCCM 2005»
15 years 3 months ago
FIFO Communication Models in Operating Systems for Reconfigurable Computing
Increasing demands upon embedded systems for higher level services like networking, user interfaces and file system management, are driving growth in fully-featured operating syst...
John A. Williams, Neil W. Bergmann, X. Xie
ISCA
2005
IEEE
119views Hardware» more  ISCA 2005»
15 years 3 months ago
Microarchitecture of a High-Radix Router
Evolving semiconductor and circuit technology has greatly increased the pin bandwidth available to a router chip. In the early 90s, routers were limited to 10Gb/s of pin bandwidth...
John Kim, William J. Dally, Brian Towles, Amit K. ...
SBCCI
2005
ACM
123views VLSI» more  SBCCI 2005»
15 years 3 months ago
Fault tolerance overhead in network-on-chip flow control schemes
Flow control mechanisms in Network-on-Chip (NoC) architectures are critical for fast packet propagation across the network and for low idling of network resources. Buffer manageme...
Antonio Pullini, Federico Angiolini, Davide Bertoz...
ADAEUROPE
2005
Springer
15 years 3 months ago
Non-intrusive System Level Fault-Tolerance
This paper describes the methodology used to add nonintrusive system-level fault tolerance to an electronic throttle controller. The original model of the throttle controller is a...
Kristina Lundqvist, Jayakanth Srinivasan, Sé...
ASYNC
2003
IEEE
73views Hardware» more  ASYNC 2003»
15 years 3 months ago
Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems
The lack of proven mechanisms for transferring data between multiple synchronous islands has been a major impediment for applying globally asynchronous locally synchronous (GALS) ...
Thomas Villiger, Hubert Kaeslin, Frank K. Gür...