857 search results - page 93 / 172 » Implementing a STARI chip |
COMPCON
1994
IEEE
15 years 1 months ago
1994
IEEE
A fully asynchronous implementation of the ARM microprocessor has been developed in order to investigate the potential of asynchronous logic for low-power applications. The work d...
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CODES
2004
IEEE
15 years 1 months ago
2004
IEEE
In this paper, a novel method for high-level specification and validation of SoC designs using UML is proposed. UML is introduced as a formal model of specification for SoC design...
CODES
2001
IEEE
15 years 1 months ago
2001
IEEE
The implementation of embedded networked appliances requires a mix of processor cores and HW accelerators on a single chip. When designing such complex and heterogeneous SoCs, the...
DAC
2005
ACM
14 years 11 months ago
2005
ACM
This paper presents an eļ¬cient hardware architecture of an on-chip logic minimization coprocessor. The proposed architecture employs TCAM cells to provide fastest and memory eļ¬...
NIPS
2001
14 years 11 months ago
2001
We have designed and fabricated a VLSI synapse that can learn a conditional probability or correlation between spike-based inputs and feedback signals. The synapse is low power, c...