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» Implementing a STARI chip
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HIPC
2007
Springer
15 years 4 months ago
Optimization of Collective Communication in Intra-cell MPI
: The Cell is a heterogeneous multi-core processor, which has eight co-processors, called SPEs. The SPEs can access a common shared main memory through DMA, and each SPE can direct...
M. K. Velamati, Arun Kumar, Naresh Jayam, Ganapath...
NOCS
2009
IEEE
15 years 4 months ago
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
This paper presents a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedd...
Anh T. Tran, Dean Truong, Bevan M. Baas
72
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ASPLOS
2010
ACM
15 years 4 months ago
Cortical architectures on a GPGPU
As the number of devices available per chip continues to increase, the computational potential of future computer architectures grows likewise. While this is a clear benefit for f...
Andrew Nere, Mikko Lipasti
ISPASS
2008
IEEE
15 years 4 months ago
Dynamic Thermal Management through Task Scheduling
The evolution of microprocessors has been hindered by their increasing power consumption and the heat generation speed on-die. High temperature impairs the processor’s reliabili...
Jun Yang 0002, Xiuyi Zhou, Marek Chrobak, Youtao Z...
MICRO
2008
IEEE
92views Hardware» more  MICRO 2008»
15 years 4 months ago
Online design bug detection: RTL analysis, flexible mechanisms, and evaluation
Higher level of resource integration and the addition of new features in modern multi-processors put a significant pressure on their verification. Although a large amount of res...
Kypros Constantinides, Onur Mutlu, Todd M. Austin