857 search results - page 98 / 172 » Implementing a STARI chip |
DAC
2000
ACM
15 years 10 months ago
2000
ACM
The Esprit/OMI-COSY project defines transaction-levels to set-up the exchange of IP's in separating function from architecture and body-behavior from proprietary interfaces. ...
107
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CALCO
2007
Springer
15 years 4 months ago
2007
Springer
Much current work on modelling and verifying microprocessors can accommodate pipelined and superscalar processors. However, superscalar and pipelined processors are no longer state...
ARC
2007
Springer
15 years 1 months ago
2007
Springer
Abstract. Conventional rigid router-based networks on chip incur certain overheads due to huge occupied logic resources and topology embedding, i.e., the mapping of a logical netwo...
ISLPED
1995
ACM
15 years 1 months ago
1995
ACM
Analog techniques can lead to ultra-efficient computational systems when applied to the right applications. The problem of associative memory is well suited to array-based analog ...
DAC
2008
ACM
15 years 10 months ago
2008
ACM
This paper presents a RTR FPGA embedded in a System on Chip fabricated in 130nm CMOS process. Various aspects of the design flow, from automation to floor-planning are discussed. ...