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ICPP
1991
IEEE
15 years 9 months ago
B-SYS: A 470-Processor Programmable Systolic Array
This paper presents an architecture for programmable systolic arrays that provides simple and e cient systolic communication. The Brown Systolic Array is a linear implementation o...
Richard Hughey, Daniel P. Lopresti
EUROPAR
2008
Springer
15 years 8 months ago
Meta-programming Applied to Automatic SMP Parallelization of Linear Algebra Code
We describe a software solution to the problem of automatic parallelization of linear algebra code on multi-processor and multi-core architectures. This solution relies on the defi...
Joel Falcou, Jocelyn Sérot, Lucien Pech, Je...
FOGA
2007
15 years 7 months ago
Neighborhood Graphs and Symmetric Genetic Operators
In the case where the search space has a group structure, classical genetic operators (mutation and two-parent crossover) which respect the group action are completely characterize...
Jonathan E. Rowe, Michael D. Vose, Alden H. Wright
SPAA
2010
ACM
15 years 4 months ago
Managing the complexity of lookahead for LU factorization with pivoting
We describe parallel implementations of LU factorization with pivoting for multicore architectures. Implementations that differ in two different dimensions are discussed: (1) usin...
Ernie Chan, Robert A. van de Geijn, Andrew Chapman
ICS
1999
Tsinghua U.
15 years 10 months ago
Realizing the performance potential of the virtual interface architecture
The Virtual Interface (VI) Architecture provides protected userlevel communication with high delivered bandwidth and low permessage latency, particularly for small messages. The V...
Evan Speight, Hazim Abdel-Shafi, John K. Bennett