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110
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HOTI
2002
IEEE
15 years 9 months ago
A Four-Terabit Single-Stage Packet Switch with Large Round-Trip Time Support
We present the architecture and practical VLSI implementation of a 4-Tb/s single-stage switch. It is based on a combined input- and crosspoint-queued structure with virtual output...
François Abel, Cyriel Minkenberg, Ronald P....
ICDCS
2002
IEEE
15 years 9 months ago
Fast Collect in the absence of contention
We present a generic module, called Fast Collect. Fast Collect is an implementation of Single-Writer Multi-Reader (SWMR) Shared-Memory in an asynchronous system in which a process...
Burkhard Englert, Eli Gafni
125
Voted
IPPS
1998
IEEE
15 years 8 months ago
Eliminating the Protocol Stack for Socket Based Communication in Shared Memory Interconnects
We show how the traditional protocol stack, such as TCP/IP, can be eliminated for socket based high speed communication within a cluster. The SCI shared memory interconnect is used...
Stein Jørgen Ryan, Haakon Bryhni
EUROPAR
2006
Springer
15 years 8 months ago
Tying Memory Management to Parallel Programming Models
Stand-alone threading libraries lack sophisticated memory management techniques. In this paper, we present a methodology that allows threading libraries that implement non-preempti...
Ioannis E. Venetis, Theodore S. Papatheodorou
165
Voted
WOB
2004
120views Bioinformatics» more  WOB 2004»
15 years 6 months ago
Reconfigurable Systems for Sequence Alignment and for General Dynamic Programming
ABSTRACT. Reconfigurable systolic arrays can be adapted to efficiently resolve a wide spectrum of computational problems; parallelism is naturally explored in systolic arrays and r...
Ricardo P. Jacobi, Mauricio Ayala-Rincón, L...