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MSO
2003
15 years 2 months ago
Simulation based Development of Efficient Hardware for Sort based Algorithms
The use of sub-optimal digital systems can at times lead to high speed, efficient, costeffective structures that are sufficient to perform needed tasks. We describe here a system ...
Niklas Hansson, Jay H. Harris
VLSISP
2008
239views more  VLSISP 2008»
15 years 1 months ago
An Embedded Real-Time Surveillance System: Implementation and Evaluation
This paper presents the design of an embedded automated digital video surveillance system with real-time performance. Hardware accelerators for video segmentation, morphological op...
Fredrik Kristensen, Hugo Hedberg, Hongtu Jiang, Pe...
IAJIT
2010
140views more  IAJIT 2010»
14 years 12 months ago
HW/SW Design-Based Implementation of Vector Median Rational Hybrid Filter
: A new code sign implementation of vector median rational hybrid filter based on efficient hardware/software implementation is introduced and applied to colour image filtering pro...
Anis Boudabous, Ahmed Ben Atitallah, Lazhar Khriji...
ESOP
2001
Springer
15 years 6 months ago
Typestate Checking of Machine Code
We check statically whether it is safe for untrusted foreign machine code to be loaded into a trusted host system. (Here “safety” means that the program abides by a memory-acc...
Zhichen Xu, Thomas W. Reps, Barton P. Miller
MICRO
2010
IEEE
202views Hardware» more  MICRO 2010»
14 years 8 months ago
Hardware Support for Relaxed Concurrency Control in Transactional Memory
Today's transactional memory systems implement the two-phase-locking (2PL) algorithm which aborts transactions every time a conflict happens. 2PL is a simple algorithm that pr...
Utku Aydonat, Tarek S. Abdelrahman