211 search results - page 22 / 43 » Implementing and Exploiting Inevitability in Software Transa... |
ISCA
1996
IEEE
15 years 1 months ago
1996
IEEE
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to addres...
ISCA
2005
IEEE
15 years 3 months ago
2005
IEEE
It has been shown that many requests miss in all remote nodes in shared memory multiprocessors. We are motivated by the observation that this behavior extends to much coarser grai...
JVCIR
2008
14 years 9 months ago
2008
This paper presents a novel hardware implementation of a disparity estimation scheme targeted to real-time Integral Photography (IP) image and video sequence compression. The soft...
177
Voted
ICDE
2005
IEEE
15 years 11 months ago
2005
IEEE
Although conventional database management systems are designed to tolerate hardware and to a lesser extent even software errors, they cannot protect themselves against syntactical...
107
Voted
MICRO
2010
IEEE
14 years 8 months ago
2010
IEEE
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...