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» Implementing communications systems on an SDR SoC
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DATE
2010
IEEE
156views Hardware» more  DATE 2010»
15 years 2 months ago
Domain specific architecture for next generation wireless communication
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...
Botao Zhang, Hengzhu Liu, Heng Zhao, Fangzheng Mo,...
CODES
2005
IEEE
15 years 3 months ago
Retargetable generation of TLM bus interfaces for MP-SoC platforms
In order to meet flexibility, performance and energy efficiency constraints, future SoC (System-on-Chip) designs will contain an increasing number of heterogeneous processor cor...
Andreas Wieferink, Rainer Leupers, Gerd Ascheid, H...
VLSID
2003
IEEE
104views VLSI» more  VLSID 2003»
15 years 3 months ago
Interfacing Cores with On-chip Packet-Switched Networks
With the emergence of the packet-switched networks as a possible system-on-chip (SoC) communication paradigm, the design of network-on-chips (NoC) has provided a challenge to the ...
Praveen Bhojwani, Rabi N. Mahapatra
IESS
2007
Springer
120views Hardware» more  IESS 2007»
15 years 3 months ago
Error Containment in the Time-Triggered System-On-a-Chip Architecture
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
Roman Obermaisser, Hermann Kopetz, Christian El Sa...
ICC
2007
IEEE
102views Communications» more  ICC 2007»
15 years 4 months ago
Frequency Domain Joint Estimation of Synchronization Parameter and Channel Impulse Response in Composite Radio Receiver
— In this paper, an innovative frequency domain joint estimation algorithm of synchronization parameter and channel impulse response (CIR) in Direct Sequence Code Division Multip...
Tianqi Wang, Cheng Li, Hsiao-Hwa Chen