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IEEEPACT
2005
IEEE
15 years 5 months ago
Design and Implementation of a Compiler Framework for Helper Threading on Multi-core Processors
Helper threading is a technique that utilizes a second core or logical processor in a multi-threaded system to improve the performance of the main thread. A helper thread executes...
Yonghong Song, Spiros Kalogeropulos, Partha Tiruma...
FPL
2003
Springer
128views Hardware» more  FPL 2003»
15 years 4 months ago
A Generic Architecture for Integrated Smart Transducers
Abstract. A smart transducer network hosts various nodes with different functionality. Our approach offers the possibility to design different smart transducer nodes as a system...
Martin Delvai, Ulrike Eisenmann, Wilfried Elmenrei...
CCECE
2006
IEEE
15 years 5 months ago
Reconfigurable Implementation of Wavelet Transform on an Fpga-Augmented NIOS Processor
The wavelet transform is a very popular tool in engineering for signal analysis. With respect to image compression, the new JPEG 2000 image standard incorporates wavelet transform...
Eugene Hyun, Mihai Sima, Michael McGuire
JSSPP
2010
Springer
14 years 9 months ago
Proposal and Evaluation of APIs for Utilizing Inter-Core Time Aggregation Scheduler
This paper proposes and evaluates APIs for Inter-Core Time Aggregation Scheduler (IAS), which is a kernel-level thread scheduler to enhance performances of multi-threaded programs ...
Satoshi Yamada, Shigeru Kusakabe
FPL
2004
Springer
106views Hardware» more  FPL 2004»
15 years 5 months ago
FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications
ASIPs and reconfigurable processors are architectural choices to extend the capabilities of a given processor. ASIPs suffer from fixed hardware after design, while ASIPs and reconf...
Leandro Möller, Ney Laert Vilar Calazans, Fer...