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» Implementing the Best Processor Cores
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IPPS
2006
IEEE
15 years 5 months ago
Exploiting unbalanced thread scheduling for energy and performance on a CMP of SMT processors
This paper explores thread scheduling on an increasingly popular architecture: chip multiprocessors with simultaneous multithreading cores. Conventional multiprocessor scheduling,...
M. De Vuyst, Rakesh Kumar, Dean M. Tullsen
IEICET
2006
84views more  IEICET 2006»
14 years 11 months ago
How to Maximize Software Performance of Symmetric Primitives on Pentium III and 4
Abstract. This paper discusses the state-of-the-art software optimization methodology for symmetric cryptographic primitives on Pentium III and 4 processors. We aim at maximizing s...
Mitsuru Matsui, Sayaka Fukuda
ISCA
2002
IEEE
82views Hardware» more  ISCA 2002»
15 years 4 months ago
Increasing Processor Performance by Implementing Deeper Pipelines
One architectural method for increasing processor performance involves increasing the frequency by implementing deeper pipelines. This paper will explore the relationship between ...
Eric Sprangle, Doug Carmean
FPL
2009
Springer
105views Hardware» more  FPL 2009»
15 years 4 months ago
Towards a viable out-of-order soft core: Copy-Free, checkpointed register renaming
As a step torward a viable, single-issue out-of-order soft core, this work presents Copy-Free Checkpointing (CFC), an FPGA-friendly register renaming design. CFC supports speculat...
Kaveh Aasaraai, Andreas Moshovos
VLSID
2006
IEEE
119views VLSI» more  VLSID 2006»
16 years 2 days ago
Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core
Performance of applications can be boosted by executing application-specific Instruction Set Extensions (ISEs) on a specialized hardware coupled with a processor core. Many commer...
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, ...