581 search results - page 14 / 117 » Implementing the Best Processor Cores |
105
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ATS
2004
IEEE
15 years 3 months ago
2004
IEEE
TIS (Test Instruction Set) is an instruction level technique for CPU core self-testing. This method is based on enhancing a CPU instruction set with test instructions. TIS replace...
MICRO
2006
IEEE
15 years 5 months ago
2006
IEEE
Growing on-chip wire delays will cause many future microarchitectures to be distributed, in which hardware resources within a single processor become nodes on one or more switched...
NCA
2009
IEEE
15 years 6 months ago
2009
IEEE
—It has been observed in recent years that in many applications service time demands are highly variable. Without foreknowledge of exact service times of individual jobs, process...
104
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ISCA
1996
IEEE
15 years 3 months ago
1996
IEEE
Simultaneous multithreading is a technique that permits multiple independent threads to issue multiple instructions each cycle. In previous work we demonstrated the performance po...
109
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TCAD
2010
14 years 6 months ago
2010
Abstract--This paper presents a GALS-compatible circuitswitched on-chip network that is well suited for use in many-core platforms targeting streaming DSP and embedded applications...