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OOPSLA
2010
Springer
14 years 10 months ago
Hera-JVM: a runtime system for heterogeneous multi-core architectures
Heterogeneous multi-core processors, such as the IBM Cell processor, can deliver high performance. However, these processors are notoriously difficult to program: different cores...
Ross McIlroy, Joe Sventek
DDECS
2008
IEEE
227views Hardware» more  DDECS 2008»
15 years 1 months ago
Cryptographic System on a Chip based on Actel ARM7 Soft-Core with Embedded True Random Number Generator
The paper introduces a cryptographic System on a Chip (SoC) implementation based on recent Actel nonvolatile FPGA Fusion chip with embedded ARM7 soft-core processor. The SoC is bui...
Milos Drutarovsky, Michal Varchola
EUROPAR
2009
Springer
15 years 4 months ago
Using Hybrid CPU-GPU Platforms to Accelerate the Computation of the Matrix Sign Function
Abstract. We investigate the performance of two approaches for matrix inversion based on Gaussian (LU factorization) and Gauss-Jordan eliminations. The target architecture is a cur...
Peter Benner, Pablo Ezzatti, Enrique S. Quintana-O...
SIGARCH
2008
107views more  SIGARCH 2008»
14 years 11 months ago
Multitasking workload scheduling on flexible core chip multiprocessors
While technology trends have ushered in the age of chip multiprocessors (CMP) and enabled designers to place an increasing number of cores on chip, a fundamental question is what ...
Divya Gulati, Changkyu Kim, Simha Sethumadhavan, S...
PDP
2008
IEEE
15 years 6 months ago
Scheduling of QR Factorization Algorithms on SMP and Multi-Core Architectures
This paper examines the scalable parallel implementation of QR factorization of a general matrix, targeting SMP and multi-core architectures. Two implementations of algorithms-by-...
Gregorio Quintana-Ortí, Enrique S. Quintana...