Sciweavers

581 search results - page 29 / 117
» Implementing the Best Processor Cores
Sort
View
EUROPAR
2010
Springer
15 years 2 months ago
Optimized Dense Matrix Multiplication on a Many-Core Architecture
Abstract. Traditional parallel programming methodologies for improving performance assume cache-based parallel systems. However, new architectures, like the IBM Cyclops-64 (C64), b...
Elkin Garcia, Ioannis E. Venetis, Rishi Khan, Guan...
IJPP
2011
105views more  IJPP 2011»
14 years 8 months ago
Correlating Radio Astronomy Signals with Many-Core Hardware
A recent development in radio astronomy is to replace traditional dishes with many small antennas. The signals are combined to form one large, virtual telescope. The enormous data ...
Rob van Nieuwpoort, John W. Romein
ISCA
2006
IEEE
182views Hardware» more  ISCA 2006»
15 years 7 months ago
Cooperative Caching for Chip Multiprocessors
This paper presents CMP Cooperative Caching, a unified framework to manage a CMP’s aggregate on-chip cache resources. Cooperative caching combines the strengths of private and ...
Jichuan Chang, Gurindar S. Sohi
SIGOPS
2010
179views more  SIGOPS 2010»
14 years 8 months ago
Online cache modeling for commodity multicore processors
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
Richard West, Puneet Zaroo, Carl A. Waldspurger, X...
99
Voted
ITNG
2007
IEEE
15 years 8 months ago
FPGA-based Vector Processing for Matrix Operations
A programmable vector processor and its implementation with a field-programmable gate array (FPGA) are presented. This processor is composed of a vector core and a tightly couple...
Hongyan Yang, Sotirios G. Ziavras, Jie Hu