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292
Voted
CODES
2004
IEEE
15 years 5 months ago
2004
IEEE
This paper proposes a novel Deadlock Avoidance Algorithm (DAA) and its hardware implementation, the Deadlock Avoidance Unit (DAU), as an Intellectual Property (IP) core that provi...
114
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CHES
2009
Springer
16 years 2 months ago
2009
Springer
We present a bitsliced implementation of AES encryption in counter mode for 64-bit Intel processors. Running at 7.59 cycles/byte on a Core 2, it is up to 25% faster than previous i...
ISLPED
1999
ACM
15 years 6 months ago
1999
ACM
In this paper, we propose a technique that uses an additional mini cache, the L0-Cache, located between the instruction cache I-Cache and the CPU core. This mechanism can provid...
137
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CORR
2011
Springer
14 years 5 months ago
2011
Springer
—Nowadays, several industrial applications are being ported to parallel architectures. These applications take advantage of the potential parallelism provided by multiple core pr...
86
Voted
DATE
2009
IEEE
15 years 8 months ago
2009
IEEE
— Modern processors are becoming more complex and as features and application size increase, their evaluation is becoming more time-consuming. To date, design space exploration r...