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CODES
2004
IEEE
15 years 10 months ago
A novel deadlock avoidance algorithm and its hardware implementation
This paper proposes a novel Deadlock Avoidance Algorithm (DAA) and its hardware implementation, the Deadlock Avoidance Unit (DAU), as an Intellectual Property (IP) core that provi...
Jaehwan Lee, Vincent John Mooney III
CHES
2009
Springer
137views Cryptology» more  CHES 2009»
16 years 6 months ago
Faster and Timing-Attack Resistant AES-GCM
We present a bitsliced implementation of AES encryption in counter mode for 64-bit Intel processors. Running at 7.59 cycles/byte on a Core 2, it is up to 25% faster than previous i...
Emilia Käsper, Peter Schwabe
ISLPED
1999
ACM
150views Hardware» more  ISLPED 1999»
15 years 10 months ago
Using dynamic cache management techniques to reduce energy in a high-performance processor
In this paper, we propose a technique that uses an additional mini cache, the L0-Cache, located between the instruction cache I-Cache and the CPU core. This mechanism can provid...
Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. P...
CORR
2011
Springer
211views Education» more  CORR 2011»
14 years 10 months ago
Programming Massively Parallel Architectures using MARTE: a Case Study
—Nowadays, several industrial applications are being ported to parallel architectures. These applications take advantage of the potential parallelism provided by multiple core pr...
Antonio Wendell De Oliveira Rodrigues, Fréd...
DATE
2009
IEEE
81views Hardware» more  DATE 2009»
16 years 26 days ago
ReSim, a trace-driven, reconfigurable ILP processor simulator
— Modern processors are becoming more complex and as features and application size increase, their evaluation is becoming more time-consuming. To date, design space exploration r...
Sotiria Fytraki, Dionisios N. Pnevmatikatos