581 search results - page 54 / 117 » Implementing the Best Processor Cores |
114
Voted
HPCA
2009
IEEE
16 years 2 months ago
2009
IEEE
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
113
Voted
ISPASS
2009
IEEE
15 years 8 months ago
2009
IEEE
Many workload characterization studies depend on accurate measurements of the cost of executing a piece of code. Often these measurements are conducted using infrastructures to ac...
113
Voted
ISVC
2009
Springer
15 years 8 months ago
2009
Springer
In this work we describe a parallel implementation of the Poisson Surface Reconstruction algorithm based on multigrid domain decomposition. We compare implementations using differ...
125
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ASPLOS
2011
ACM
14 years 5 months ago
2011
ACM
The adoption of transactional memory is hindered by the high overhead of software transactional memory and the intrusive design changes required by previously proposed TM hardware...
EUROPAR
2007
Springer
15 years 8 months ago
2007
Springer
1 Future gain in computing performance will not stem from increased clock rates, but from even more cores in a processor. Since automatic parallelization is still limited to easily...