Sciweavers

581 search results - page 57 / 117
» Implementing the Best Processor Cores
Sort
View
ERSA
2009
131views Hardware» more  ERSA 2009»
14 years 11 months ago
Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays
An effective way to implement image processing applications is to use embedded processors with dynamically reconfigurable accelerator cores. The processing speed of these processor...
Hasitha Muthumala Waidyasooriya, Masanori Hariyama...
IPPS
2005
IEEE
15 years 7 months ago
Broadcast Trees for Heterogeneous Platforms
In this paper, we deal with broadcasting on heterogeneous platforms. Typically, the message to be broadcast is split into several slices, which are sent by the source processor in...
Olivier Beaumont, Loris Marchal, Yves Robert
MICRO
2006
IEEE
84views Hardware» more  MICRO 2006»
15 years 8 months ago
Reunion: Complexity-Effective Multicore Redundancy
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
Jared C. Smolens, Brian T. Gold, Babak Falsafi, Ja...
CGO
2009
IEEE
15 years 8 months ago
Computer Generation of General Size Linear Transform Libraries
The development of high-performance libraries has become extraordinarily difficult due to multiple processor cores, vector instruction sets, and deep memory hierarchies. Often, t...
Yevgen Voronenko, Frédéric de Mesmay...
DATE
2008
IEEE
102views Hardware» more  DATE 2008»
15 years 8 months ago
Vectorization of Reed Solomon Decoding and Mapping on the EVP
Reed Solomon (RS) codes are used in a variety of (wireless) communication systems. Although commonly implemented in dedicated hardware, this paper explores the mapping of high-thr...
Akash Kumar, Kees van Berkel