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» Implementing the Best Processor Cores
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PDP
2009
IEEE
15 years 8 months ago
Phoenix: A Runtime Environment for High Performance Computing on Chip Multiprocessors
Abstract—Execution of applications on upcoming highperformance computing (HPC) systems introduces a variety of new challenges and amplifies many existing ones. These systems will...
Avneesh Pant, Hassan Jafri, Volodymyr V. Kindraten...
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
15 years 7 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
CASCON
2004
127views Education» more  CASCON 2004»
15 years 3 months ago
A quantitative analysis of the performance impact of specialized bytecodes in java
Java is implemented by 201 bytecodes that serve the same purpose as assembler instructions while providing object-file platform independence. A collection of core bytecodes provid...
Ben Stephenson, Wade Holst
MICRO
2009
IEEE
168views Hardware» more  MICRO 2009»
15 years 8 months ago
Ordering decoupled metadata accesses in multiprocessors
Hardware support for dynamic analysis can minimize the performance overhead of useful applications such as security checks, debugging, and profiling. To eliminate implementation ...
Hari Kannan
IPPS
2009
IEEE
15 years 8 months ago
Scaling communication-intensive applications on BlueGene/P using one-sided communication and overlap
In earlier work, we showed that the one-sided communication model found in PGAS languages (such as UPC) offers significant advantages in communication efficiency by decoupling d...
Rajesh Nishtala, Paul Hargrove, Dan Bonachea, Kath...