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» Implementing the Best Processor Cores
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103
Voted
DSD
2009
IEEE
118views Hardware» more  DSD 2009»
15 years 5 months ago
On the Risk of Fault Coupling over the Chip Substrate
—Duplication and comparison has proven to be an efficient method for error detection. Based on this generic principle dual core processor architectures with output comparison ar...
Peter Tummeltshammer, Andreas Steininger
ISCA
2008
IEEE
170views Hardware» more  ISCA 2008»
15 years 8 months ago
Polymorphic On-Chip Networks
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...
Martha Mercaldi Kim, John D. Davis, Mark Oskin, To...
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
15 years 8 months ago
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Increasing miniaturization is posing multiple challenges to electronic designers. In the context of Multi-Processor System-onChips (MPSoCs), we focus on the problem of implementin...
Federico Angiolini, Paolo Meloni, Salvatore Carta,...
120
Voted
DATE
2005
IEEE
133views Hardware» more  DATE 2005»
15 years 7 months ago
Locality-Aware Process Scheduling for Embedded MPSoCs
Utilizing on-chip caches in embedded multiprocessorsystem-on-a-chip (MPSoC) based systems is critical from both performance and power perspectives. While most of the prior work th...
Mahmut T. Kandemir, Guilin Chen
IMC
2010
ACM
14 years 11 months ago
High speed network traffic analysis with commodity multi-core systems
Multi-core systems are the current dominant trend in computer processors. However, kernel network layers often do not fully exploit multi-core architectures. This is due to issues...
Francesco Fusco, Luca Deri