Sciweavers

141 search results - page 18 / 29
» Implications of technology scaling on leakage reduction tech...
Sort
View
CF
2005
ACM
14 years 11 months ago
Exploiting temporal locality in drowsy cache policies
Technology projections indicate that static power will become a major concern in future generations of high-performance microprocessors. Caches represent a significant percentage ...
Salvador Petit, Julio Sahuquillo, Jose M. Such, Da...
CF
2007
ACM
15 years 1 months ago
Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors
Energy-efficient microprocessor designs are one of the major concerns in both high performance and embedded processor domains. Furthermore, as process technology advances toward d...
Juan M. Cebrian, Juan L. Aragón, José...
DSN
2008
IEEE
14 years 11 months ago
An accurate flip-flop selection technique for reducing logic SER
The combination of continued technology scaling and increased on-chip transistor densities has made vulnerability to radiation induced soft errors a significant design concern. In...
Eric L. Hill, Mikko H. Lipasti, Kewal K. Saluja
ISLPED
2003
ACM
149views Hardware» more  ISLPED 2003»
15 years 2 months ago
Elements of low power design for integrated systems
The increasing prominence of portable systems and the need to limit power consumption and hence, heat dissipation in very high density VLSI chips have led to rapid and innovative ...
Sung-Mo Kang
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Frequency Selective Model Order Reduction via Spectral Zero Projection
As process technology continues to scale into the nanoscale regime, interconnect plays an ever increasing role in determining VLSI system performance. As the complexity of these sy...
Mehboob Alam, Arthur Nieuwoudt, Yehia Massoud