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ICCD
2004
IEEE
100views Hardware» more  ICCD 2004»
15 years 6 months ago
Thermal-Aware Clustered Microarchitectures
As frequencies and feature size scale faster than operating voltages, power density is increasing in each processor generation. Power density and the cost of removing the heat it ...
Pedro Chaparro, José González, Anton...
TVLSI
2008
153views more  TVLSI 2008»
14 years 9 months ago
Characterization of a Novel Nine-Transistor SRAM Cell
Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors...
Zhiyu Liu, Volkan Kursun
ISCAS
2007
IEEE
90views Hardware» more  ISCAS 2007»
15 years 3 months ago
Leakage-Aware Design of Nanometer SoC
– In the sub-65 nm CMOS technologies, subthreshold and gate dielectric leakage currents need to be simultaneously suppressed for effective energy reduction. New low-leakage circu...
Volkan Kursun, Sherif A. Tawfik, Zhiyu Liu
CASES
2007
ACM
15 years 1 months ago
Cache leakage control mechanism for hard real-time systems
Leakage energy consumption is an increasingly important issue as the technology continues to shrink. Since on-chip caches constitute a major portion of the processor's transi...
Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia...
ICCAD
2003
IEEE
152views Hardware» more  ICCAD 2003»
15 years 6 months ago
Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
Nam Sung Kim, David Blaauw, Trevor N. Mudge