64 search results - page 10 / 13 » Improve Chip Pin Performance Using Optical Interconnects |
AINA
2007
IEEE
15 years 5 months ago
2007
IEEE
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...
DAC
2006
ACM
16 years 12 days ago
2006
ACM
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...
ISCA
2006
IEEE
15 years 5 months ago
2006
IEEE
Prior research indicates that there is much spatial variation in applications' memory access patterns. Modern memory systems, however, use small fixed-size cache blocks and a...
DATE
2006
IEEE
15 years 5 months ago
2006
IEEE
This paper explores optimization techniques of the synchronization mechanisms for MPSoCs based on complex interconnect (Network-on-Chip), targeted at future powerefficient system...
DAC
2005
ACM
16 years 12 days ago
2005
ACM
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been...