64 search results - page 5 / 13 » Improve Chip Pin Performance Using Optical Interconnects |
ICCD
2006
IEEE
15 years 8 months ago
2006
IEEE
— The influence of interconnects on processor performance and cost is becoming increasingly pronounced with technology scaling. In this paper, we present a fast compression sche...
JETC
2008
14 years 10 months ago
2008
With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a severe issue in to...
GLOBECOM
2007
IEEE
15 years 5 months ago
2007
IEEE
: We describe a coded power-efficient transmission scheme based on repetition MIMO principle suitable for communication over the atmospheric turbulence channel, and determine its c...
113
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SBCCI
2005
ACM
15 years 5 months ago
2005
ACM
Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congesti...
103
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TC
1998
14 years 11 months ago
1998
—The very high levels of integration and submicron device sizes used in current and emerging VLSI technologies for FPGAs lead to higher occurrences of defects and operational fau...