64 search results - page 6 / 13 » Improve Chip Pin Performance Using Optical Interconnects |
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FGCS
2007
14 years 11 months ago
2007
Clusters of computers have emerged as cost-effective parallel and/or distributed computing systems for computationally intensive tasks. Normally, clusters are composed of high per...
ICCAD
1997
IEEE
15 years 3 months ago
1997
IEEE
Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends...
PDP
2010
IEEE
15 years 3 months ago
2010
IEEE
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
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DAC
2000
ACM
16 years 12 days ago
2000
ACM
Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the ...
ISCA
2008
IEEE
14 years 11 months ago
2008
IEEE
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...