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» Improved Algorithms for the 2-Vertex Disjoint Paths Problem
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DATE
2007
IEEE
114views Hardware» more  DATE 2007»
15 years 6 months ago
Two-level microprocessor-accelerator partitioning
The integration of microprocessors and field-programmable gate array (FPGA) fabric on a single chip increases both the utility and necessity of tools that automatically move softw...
Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank V...
DAC
1994
ACM
15 years 3 months ago
Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture
- This paper studies the routing problem for a new Field-Programmable Gate Array (FPGA) and Field-Programmable Interconnect Chip (FPIC) routing architecture which improves upon the...
Yachyang Sun, C. L. Liu
ALGOSENSORS
2009
Springer
15 years 3 months ago
Routing on Delay Tolerant Sensor Networks
Abstract. Delay (or disruption) tolerant sensor networks may be modeled as Markovian evolving graphs [1]. We present experimental evidence showing that considering multiple (possib...
Michael Keane, Evangelos Kranakis, Danny Krizanc, ...
SARA
2007
Springer
15 years 5 months ago
Computing and Using Lower and Upper Bounds for Action Elimination in MDP Planning
Abstract. We describe a way to improve the performance of MDP planners by modifying them to use lower and upper bounds to eliminate non-optimal actions during their search. First, ...
Ugur Kuter, Jiaqiao Hu
DAGSTUHL
2007
15 years 1 months ago
Implementing RPO and POLO using SAT
Abstract. Well-founded orders are the most basic, but also most important ingredient to virtually all termination analyses. Numerous fully automated search algorithms for these cla...
Peter Schneider-Kamp, Carsten Fuhs, René Th...