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DAC
2010
ACM
15 years 1 months ago
TSV stress aware timing analysis with applications to 3D-IC layout optimization
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee,...
VLDB
2002
ACM
141views Database» more  VLDB 2002»
15 years 10 months ago
Data page layouts for relational databases on deep memory hierarchies
Relational database systems have traditionally optimized for I/O performance and organized records sequentially on disk pages using the N-ary Storage Model (NSM) (a.k.a., slotted ...
Anastassia Ailamaki, David J. DeWitt, Mark D. Hill
ICDAR
2009
IEEE
15 years 4 months ago
Text Lines and Snippets Extraction for 19th Century Handwriting Documents Layout Analysis
In this paper we propose a new approach to improve electronic editions of human science corpus, providing an efficient estimation of manuscripts pages structure. In any handwriti...
Vincent Malleron, Véronique Eglin, Hubert E...
ACSAC
2006
IEEE
15 years 3 months ago
Address Space Layout Permutation (ASLP): Towards Fine-Grained Randomization of Commodity Software
Address space randomization is an emerging and promising method for stopping a broad range of memory corruption attacks. By randomly shifting critical memory regions at process in...
Chongkyung Kil, Jinsuk Jun, Christopher Bookholt, ...
ICCAD
2003
IEEE
170views Hardware» more  ICCAD 2003»
15 years 6 months ago
Evaluation of Placement Techniques for DNA Probe Array Layout
DNA probe arrays have emerged as a core genomic technology that enables cost-effective gene expression monitoring, mutation detection, single nucleotide polymorphism analysis and ...
Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu ...