525 search results - page 35 / 105 » Improved Circular Layouts |
IV
2007
IEEE
15 years 4 months ago
2007
IEEE
We consider routing methods for networks when geographic positions of nodes are available. Instead of using the original geographic coordinates, however, we precompute virtual coo...
DSD
2006
IEEE
15 years 3 months ago
2006
IEEE
Programmable logic arrays (PLAs) present an alternative to logic-gate based design. We propose the transistor level structure of a PLA for single-rail asynchronous applications. T...
EURODAC
1994
IEEE
15 years 1 months ago
1994
IEEE
Clock routing has become a critical issue in the layout design of high-performance systems. We show that the two passes bottom-up and top-down of the DME algorithm 2, 3, 4, 8 can ...
ASPDAC
2005
ACM
14 years 11 months ago
2005
ACM
- Redundant via insertion is a good solution to reduce the yield loss by via failure. However, the existing methods are all post-layout optimizations that insert redundant via afte...
WSC
1997
14 years 11 months ago
1997
Robert C. Byrd Hardwood Technology Center R.R. 2, Box 556 Princeton, WV 24740, U.S.A. Lumber processing simulation allows the user an opportunity to examine ways to best utilize t...