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DATE
2003
IEEE
103views Hardware» more  DATE 2003»
15 years 5 months ago
Area Fill Generation With Inherent Data Volume Reduction
Control of variability and performance in the back end of the VLSI manufacturing line has become extremely difficult with the introduction of new materials such as copper and low...
Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexande...
DATE
2003
IEEE
103views Hardware» more  DATE 2003»
15 years 5 months ago
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
Dimitrios Velenis, Marios C. Papaefthymiou, Eby G....
DAC
1999
ACM
15 years 4 months ago
Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design
As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bu...
Joon-Seo Yim, Chong-Min Kyung
IFIP
1999
Springer
15 years 4 months ago
Frontier: A Fast Placement System for FPGAs
In this paper we describe Frontier, an FPGA placement system that uses design macro-blocks in conjuction with a series of placement algorithms to achieve highly-routable and high-...
Russell Tessier
EP
1998
Springer
15 years 4 months ago
Memory Scalability in Constraint-Based Multimedia Style Sheet Systems
Abstract. Multimedia style sheet systems uniformly use a constraintbased model of layout. Constraints provide a uniform mechanism for all aspects of style management and layout and...
Terry Cumaranatunge, Ethan V. Munson