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ICCAD
2009
IEEE
118views Hardware» more  ICCAD 2009»
15 years 2 months ago
Pre-bond testable low-power clock tree design for 3D stacked ICs
Pre-bond testing of 3D stacked ICs involves testing individual dies before bonding. The overall yield of 3D ICs improves with prebond testability because designers can avoid stack...
Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung K...
ICCAD
2009
IEEE
132views Hardware» more  ICCAD 2009»
15 years 2 months ago
DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
Lu Wan, Deming Chen
ICCAD
2009
IEEE
151views Hardware» more  ICCAD 2009»
15 years 2 months ago
Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography
Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, ...
Mohit Gupta, Kwangok Jeong, Andrew B. Kahng
ICDE
2009
IEEE
173views Database» more  ICDE 2009»
15 years 2 months ago
Efficient Mining of Closed Repetitive Gapped Subsequences from a Sequence Database
There is a huge wealth of sequence data available, for example, customer purchase histories, program execution traces, DNA, and protein sequences. Analyzing this wealth of data to ...
Bolin Ding, David Lo, Jiawei Han, Siau-Cheng Khoo
ICDM
2009
IEEE
172views Data Mining» more  ICDM 2009»
15 years 2 months ago
Evaluating Statistical Tests for Within-Network Classifiers of Relational Data
Recently a number of modeling techniques have been developed for data mining and machine learning in relational and network domains where the instances are not independent and ide...
Jennifer Neville, Brian Gallagher, Tina Eliassi-Ra...
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