100 search results - page 13 / 20 » Improved Policies for Drowsy Caches in Embedded Processors |
SBCCI
2005
ACM
15 years 5 months ago
2005
ACM
Code compression, initially conceived as an effective technique to reduce code size in embedded systems, today also brings advantages in terms of performance and energy consumpti...
SAMOS
2007
Springer
15 years 5 months ago
2007
Springer
Abstract—Most research work on (Simultaneous Multithreading Processors) SMTs focuses on improving throughput and/or fairness, or on prioritizing some threads over others in a wor...
ISLPED
2003
ACM
15 years 5 months ago
2003
ACM
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
101
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ECRTS
1998
IEEE
15 years 4 months ago
1998
IEEE
This paper introduces improvements in partitioning schemes for multiprocessor real-time systems which allow higher processor utilization and enhanced schedulability by using exact...
100
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RTSS
2003
IEEE
15 years 5 months ago
2003
IEEE
This paper presents a quantification of the timing effects that advanced processor features like data and instruction cache, pipelines, branch prediction units and out-oforder ex...