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» Improved Policies for Drowsy Caches in Embedded Processors
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CASES
2003
ACM
15 years 4 months ago
Frequent loop detection using efficient non-intrusive on-chip hardware
Dynamic software optimization methods are becoming increasingly popular for improving software performance and power. The first step in dynamic optimization consists of detecting ...
Ann Gordon-Ross, Frank Vahid
RTAS
1996
IEEE
15 years 3 months ago
Efficient worst case timing analysis of data caching
Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching, which is necessa...
Sung-Kwan Kim, Sang Lyul Min, Rhan Ha
HPCA
1995
IEEE
15 years 3 months ago
Software Cache Coherence for Large Scale Multiprocessors
Shared memory is an appealing abstraction for parallel programming. It must be implemented with caches in order toperform well, however, and caches require a coherence mechanism t...
Leonidas I. Kontothanassis, Michael L. Scott
SIGARCH
2008
97views more  SIGARCH 2008»
14 years 11 months ago
SP-NUCA: a cost effective dynamic non-uniform cache architecture
1 This paper presents a simple but effective method to reduce on-chip access latency and improve core isolation in CMP Non-Uniform Cache Architectures (NUCA). The paper introduces ...
Javier Merino, Valentin Puente, Pablo Prieto, Jos&...
82
Voted
IPPS
2000
IEEE
15 years 4 months ago
Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...
Ravi R. Iyer, Laxmi N. Bhuyan, Ashwini K. Nanda