100 search results - page 17 / 20 » Improved Policies for Drowsy Caches in Embedded Processors |
AINA
2007
IEEE
15 years 6 months ago
2007
IEEE
The widening gap between CPU and memory speed has made caches an integral feature of modern highperformance processors. The high degree of configurability of cache memory can requ...
MICRO
2007
IEEE
15 years 6 months ago
2007
IEEE
The trends in enterprise IT toward service-oriented computing, server consolidation, and virtual computing point to a future in which workloads are becoming increasingly diverse i...
ICCD
2004
IEEE
15 years 8 months ago
2004
IEEE
Speculative Multi-Threading (SpMT) can improve single-threaded application performance using the multiple thread contexts available in current processors. We propose a minimal SpM...
110
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NOCS
2007
IEEE
15 years 6 months ago
2007
IEEE
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
101
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CASES
2010
ACM
14 years 9 months ago
2010
ACM
Dynamic binary translators (DBTs) are becoming increasingly important because of their power and flexibility. However, the high memory demands of DBTs present an obstacle for all ...