100 search results - page 9 / 20 » Improved Policies for Drowsy Caches in Embedded Processors |
121
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RTAS
2011
IEEE
14 years 2 months ago
2011
IEEE
—It is widely assumed that scheduling real-time tasks becomes more difficult as their deadlines get shorter. With deadlines shorter, however, tasks potentially compete less with...
ISCA
2007
IEEE
15 years 6 months ago
2007
IEEE
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...
114
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DAC
2010
ACM
14 years 12 months ago
2010
ACM
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
VLSID
2006
IEEE
16 years 2 days ago
2006
IEEE
- Security protocols, such as IPSec and SSL, are being increasingly deployed in the context of networked embedded systems. The resource-constrained nature of embedded systems and, ...
ISCA
2010
IEEE
15 years 4 months ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...