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» Improved Simulation of Stabilizer Circuits
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ISCAS
2005
IEEE
130views Hardware» more  ISCAS 2005»
15 years 3 months ago
RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction
Inductance effects of on-chip interconnects have become more and more significant in today’s high-speed digital circuits, especially for global interconnects such as signal buse...
Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang
DATE
2006
IEEE
88views Hardware» more  DATE 2006»
15 years 4 months ago
Timing-reasoning-based delay fault diagnosis
In this paper, we propose a timing-reasoning algorithm to improve the resolution of delay fault diagnosis. In contrast to previous approaches which identify candidates by utilizin...
Kai Yang, Kwang-Ting Cheng
GLVLSI
2003
IEEE
146views VLSI» more  GLVLSI 2003»
15 years 3 months ago
A practical CAD technique for reducing power/ground noise in DSM circuits
One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In...
Arindam Mukherjee, Krishna Reddy Dusety, Rajsaktis...
GECCO
2004
Springer
100views Optimization» more  GECCO 2004»
15 years 3 months ago
Transfer of Neuroevolved Controllers in Unstable Domains
In recent years, the evolution of artificial neural networks or neuroevolution has brought promising results in solving difficult reinforcement learning problems. But, like standa...
Faustino J. Gomez, Risto Miikkulainen
DAC
2005
ACM
14 years 12 months ago
A combined feasibility and performance macromodel for analog circuits
The need to reuse the performance macromodels of an analog circuit topology challenges existing regression based modeling techniques. A model of good reusability should have a num...
Mengmeng Ding, Ranga Vemuri