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ICCAD
1995
IEEE
68views Hardware» more  ICCAD 1995»
15 years 1 months ago
Generating sparse partial inductance matrices with guaranteed stability
This paper proposes a definition of magnetic vector potential that can be used to evaluate sparse partial inductance matrices. Unlike the commonly applied procedure of discarding...
Byron Krauter, Lawrence T. Pileggi
DSD
2005
IEEE
105views Hardware» more  DSD 2005»
15 years 3 months ago
Improved Fault Emulation for Synchronous Sequential Circuits
Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subta...
Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, R...
LATIN
2010
Springer
15 years 4 months ago
The Size and Depth of Layered Boolean Circuits
We consider the relationship between size and depth for layered Boolean circuits, synchronous circuits and planar circuits as well as classes of circuits with small separators. In ...
Anna Gál, Jing-Tang Jang
ASPDAC
2004
ACM
105views Hardware» more  ASPDAC 2004»
15 years 3 months ago
Improved symbolic simulation by functional-space decomposition
Abstract — This paper presents a functional-space decomposition approach to enhance the capability of symbolic simulation. In our symbolic simulator, the control part and datapat...
Tao Feng, Li-C. Wang, Kwang-Ting Cheng
ISQED
2007
IEEE
136views Hardware» more  ISQED 2007»
15 years 4 months ago
Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS
Straining of silicon improves mobility of carriers resulting in speed enhancement for transistors in CMOS technology. Traditionally, silicon straining is applied in a similar ad-h...
Rajani Kuchipudi, Hamid Mahmoodi