Sciweavers

376 search results - page 43 / 76
» Improved Simulation of Stabilizer Circuits
Sort
View
ISLPED
2003
ACM
90views Hardware» more  ISLPED 2003»
15 years 3 months ago
Understanding and minimizing ground bounce during mode transition of power gating structures
We introduce and analyze the ground bounce due to power mode transition in power gating structures. To reduce the ground bounce, we propose novel power gating structures in which ...
Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel
APCCAS
2002
IEEE
138views Hardware» more  APCCAS 2002»
15 years 2 months ago
A 2.5-V 10-bit 40-MS/S double sampling pipeline A/D converter
This paper presents a 10-bit pipeline ADC using double sampling technique to achieve a conversion rate of 40 MS/s at 2.5-V supply. The opamps are two-stage with folded-cascode as ...
A. Tamtrakarn, N. Wongkomet
ASPDAC
2005
ACM
93views Hardware» more  ASPDAC 2005»
14 years 12 months ago
Power minimization for dynamic PLAs
—Dynamic programmable logic arrays (PLAs) which are built of the NOR–NOR structure, have been very popular in high performance design because of their high-speed and predictabl...
Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, ...
TCAD
2008
136views more  TCAD 2008»
14 years 10 months ago
A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved i...
Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar
ICCD
2005
IEEE
116views Hardware» more  ICCD 2005»
15 years 6 months ago
Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis
Consideration of pairs of transition in probabilistic simulation allows power estimation for digital circuits in which inertial delays can filter glitches [5]. However, the merit ...
Fei Hu, Vishwani D. Agrawal