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ICCAD
2001
IEEE
108views Hardware» more  ICCAD 2001»
15 years 6 months ago
Placement Driven Retiming with a Coupled Edge Timing Model
Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear, whether the pred...
Ingmar Neumann, Wolfgang Kunz
ISLPED
2006
ACM
140views Hardware» more  ISLPED 2006»
15 years 3 months ago
L-CBF: a low-power, fast counting bloom filter architecture
—An increasing number of architectural techniques rely on hardware counting bloom filters (CBFs) to improve upon the enegy, delay and complexity of various processor structures. ...
Elham Safi, Andreas Moshovos, Andreas G. Veneris
ISCAS
1999
IEEE
131views Hardware» more  ISCAS 1999»
15 years 2 months ago
A multilevel modulation scheme for high-speed wireless infrared communications
To investigate short-distance, point-to-point, infrared channels, a test-bench and circuits were constructed to determine the limitations ofexisting optoelectronics. Theresults of...
S. Hranilovic, D. A. Johns
DAC
1994
ACM
15 years 2 months ago
Simultaneous Placement and Module Optimization of Analog IC's
New placement techniques are presented which substantially improve the process of automatic layout generation of analog IC's. Extremely tight specifications can be enforced o...
Edoardo Charbon, Enrico Malavasi, Davide Pandini, ...
HPCA
2005
IEEE
15 years 10 months ago
Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors
Dynamic voltage and frequency scaling (DVFS) is a widely-used method for energy-efficient computing. In this paper, we present a new intra-task online DVFS scheme for multiple clo...
Qiang Wu, Philo Juang, Margaret Martonosi, Douglas...