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» Improved Simulation of Stabilizer Circuits
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ICON
2007
IEEE
15 years 4 months ago
Erlang B as a Performance Model for IP Flows
— Flow-based networking has gained momentum in the research community in recent years. It allows improved performance guarantees and dynamic, load-aware routing. Flowbased networ...
Alexander A. Kist
ISCAS
2003
IEEE
172views Hardware» more  ISCAS 2003»
15 years 3 months ago
Performance modeling of resonant tunneling based RAMs
Tunneling based random-access memories (TRAM’s) have recently garnered a great amount of interests among the memory designers due to their intrinsic merits such as reduced power...
Hui Zhang, Pinaki Mazumder, Li Ding 0002, Kyoungho...
DATE
2010
IEEE
170views Hardware» more  DATE 2010»
15 years 3 months ago
Analytical model for TDDB-based performance degradation in combinational logic
With aggressive gate oxide scaling, latent defects in the gate oxide manifest as traps that, in time, lead to gate oxide breakdown. Progressive gate oxide breakdown, also referred...
Mihir Choudhury, Vikas Chandra, Kartik Mohanram, R...
ISQED
2002
IEEE
129views Hardware» more  ISQED 2002»
15 years 2 months ago
Design Method and Automation of Comparator Generation for Flash A/D Converter
The design methods and the automation of the comparator circuit layout generation for a flash A/D converter are presented in this paper. The threshold inverter quantization (TIQ)...
Daegyu Lee, Jincheol Yoo, Kyusun Choi
ISQED
2000
IEEE
91views Hardware» more  ISQED 2000»
15 years 2 months ago
Probabilistic Bottom-Up RTL Power Estimation
We address the problem of power estimation at the register-transfer level (RTL). At this level, the circuit is described in terms of a set of interconnected memory elements and co...
Ricardo Ferreira, A.-M. Trullemans, José C....